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White Electronic Designs
WED3DG7264V-D1
PRELIMINARY*
512MB - 2x32Mx72 SDRAM, UNBUFFERED w/PLL
FEATURES
Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmable Burst Lengths: 1, 2, 4, 8 or Full Page 3.3V 0.3V Power Supply 144 Pin SO-DIMM * D1: 31.75mm (1.25")
DESCRIPTION
The WED3DG7264V is a 2x32Mx72 synchronous DRAM module which consists of eighteen 32Mx8 stack SDRAM components in TSOP II package, and one 2Kb EEPROM in an 8 pin TSSOP package for Serial Presence Detect which are mounted on a 144 pin SO-DIMM multilayer FR4 Substrate.
* This product is under development, is not qualified or characterized and is subject to change without notice. NOTE: Consult factory for availability of: * RoHS compliant products * Vendor source control options * Industrial temperature option
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PINOUT PIN 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 FRONT VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 VSS DQM0 DQM1 VCC A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VCC DQ12 PIN 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 BACK VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 VSS DQM4 DQM5 VCC A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VCC DQ44 PIN 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 FRONT DQ13 DQ14 DQ15 VSS CB0 CB1 CLK0 VCC RAS# WE# CS0# CS1# NC VSS CB2 CB3 VCC DQ16 DQ17 DQ18 DQ19 VSS DQ20 DQ21 PIN 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 BACK DQ45 DQ46 DQ47 VSS CB4 CB5 CKE0 VCC CAS# CKE1 A12 NC NC VSS CB6 CB7 VCC DQ48 DQ49 DQ50 DQ51 VSS DQ52 DQ53 PIN 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 FRONT DQ22 DQ23 VCC A6 A8 VSS A9 A10 VCC DQM2 DQM3 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS SDA VCC PIN 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 BACK DQ54 DQ55 VCC A7 BA0 VSS BA1 A11 VCC DQM6 DQM7 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS SCL VCC
A0 - A12 BA0-1 DQ0-63 CLK0 CB0-7 CKE0,CKE1 CS0#,CS1# RAS# CAS# WE# DQM0-7 VCC VSS SDA SCL DNU NC
PIN NAMES
Address Input (Multiplexed) Select Bank Data Input/Output Clock Input Check Bit (Data-In/Data-Out) Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe Write Enable DQM Power Supply (3.3V) Ground Serial Data I/O Serial Clock Do Not Use No Connect
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 4 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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FUNCTIONAL BLOCK DIAGRAM
CS1# WE# CS0# DQM0
DQM S
WED3DG7264V-D1
PRELIMINARY
*
DQM4
WE# DQM S WE# DQM S WE# DQM S WE#
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DQM S I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQM S WE#
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DQM S I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQM S WE#
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM6
WE#
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DQM S I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 WE#
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DQM S I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 WE#
WE#
DQM S
WE#
DQM S
WE#
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DQM S I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
WE#
DQM S I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
WE#
DQM S
WE#
DQM S
WE#
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
DQM S
WE#
DQM S
WE#
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CLK0
PLL
SDRAM
NOTE: DQ wiring may differ than described in this drawing, however DQ/DQMB/CKE/S relationships must be maintained as shown.
RAS# CAS# CKE0 CKE1 BA0-BA1 A0-A12 VCC VSS
RAS#: SDRAM CAS#: SDRAM CKE0: SDRAM CKE1: SDRAM BA0-BA1: SDRAM A0-A12: SDRAM SDRAM SDRAM
SERIAL PD SCL A0 A1 A2 SDA
Note: All resistor values are 10 ohms unless otherwise specified.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 4 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS
WED3DG7264V-D1
PRELIMINARY
Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 9 50
Units V V C W mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: VSS = 0V, 0C TA +70C Parameter Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Symbol VCC VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -- -10 Typ 3.3 3.0 -- -- -- -- Max 3.6 VCCQ+0.3 0.8 -- 0.4 10 Unit V V V V V A 1 2 IOH= -2mA IOL= + 2mA 3 Note
Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min)= -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VCCQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
TA 25C, f = 1MHz, VCC = 3.3V, VREF = 1.4V 200mV
Parameter Input Capacitance (A0-A12) Input Capacitance (RAS#,CAS#,WE#) Input Capacitance (CKE0) Input Capacitance (CLK0) Input Capacitance (CS0#) Input Capacitance (DQM0-DQM7) Input Capacitance (BA0-BA1) Data Input/Output Capacitance (DQ0-DQ63) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT Max 74 74 40 5.5 40 11 74 15 Unit pF pF pF pF pF pF pF pF
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 4 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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OPERATING CURRENT CHARACTERISTICS
VCC = 3.3V 0.3V, 0C TA +70C
WED3DG7264V-D1
PRELIMINARY
Version Parameter Operating Current (One bank active) Precharge Standby Current in Power Down Mode Active Standby Current in Power-Down Mode Symbol ICC1 Conditions Burst Length = 1 tRC tRC(min) IOL = 0mA CKE VIL(max), tCC = 10ns CKE VIL(max), tCC = 10ns Io = mA Page burst 4 Banks activated tCCD = 2CK tRC tRC(min) CKE 0.2V 100/133 1,620 Units mA Note 1
ICC2 ICC3 ICC4
35 540
mA mA
Operating Current (Burst mode)
1,800
mA
1
Refresh Current Self Refresh Current
Notes: 1. Measured with outputs open. 2. Refresh period is 64ms.
ICC5 ICC6
3,600 110
mA mA
2
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 4 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
VCC = 3.3V 0.3V, 0C TA +70C AC CHARACTERISTICS PARAMETER Access time from CLK (pos. edge) CL = 3 CL = 2 Address hold time Address setup time CLK high-level width CLK low-level width Clock cycle time CL = 3 CL = 2 CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out high-impedance time CL = 3 CL = 2 Data-out low-impedance time Data-out hold time (load) Data-out hold time (no load) ACTIVE to PRECHARGE command ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay Refresh period (8,192 rows) AUTO REFRESH period PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time WRITE recovery time SYMBOL tAC(3) tAC(2) tAH tAS tCH tCL tCK(3) tCK(2) tCKH tCKS tCMH tCMS tDH tDS tHZ(3) tHZ(2) tLZ tOH tOHN tRAS tRC tRCD tREF tRFC tRP tRRD tT tWR 66 15 14 0.3 1 CLK + 7ns 14 Exit SELF REFRESH to ACTIVE command tXSR 67 1.2 1 2.7 1.8 37 60 15 64 120K 0.8 1.5 2.5 2.5 7 7.5 0.8 1.5 0.8 1.5 0.8 1.5 5.4 5.4 MIN 7 MAX 5.4 5.4
WED3DG7264V-D1
PRELIMINARY
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
75/10 MIN MAX 5.4 6 0.8 1.5 2.5 2.5 7.5 10 0.8 1.5 0.8 1.5 0.8 1.5 5.4 6 1 2.7 1.8 44 66 20 64 66 20 15 0.3 1 CLK + 7ns 15 75 1.2 120K UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns 7 24 14, 25 20 28 10 10 23 23 NOTES 27
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 4 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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AC FUNCTIONAL CHARACTERISTICS
VCC = 3.3V 0.3V, 0C TA +70C PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQM to data high-impedance during READs WRITE command to input data delay Data-in to ACTIVE command Data-in to PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command CL = 3 CL = 2 SYMBOL tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL tDPL tBDL tCDL tRDL tMRD tROH(3) tROH(2) 7 1 1 1 0 0 2 0 4 2 1 1 2 2 3 2
WED3DG7264V-D1
PRELIMINARY
75/10 1 1 1 0 0 2 0 5 2 1 1 2 2 3 2
UNITS tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK tCK
NOTES 17 14 14 17 17 17 17 15, 21 16, 21 17 17 16, 21 26 17 17
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 4 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Notes 1. All voltages referenced to VSS. 2. This parameter is sampled. VCC, VCCQ = +3.3V; = 25C; pin under test biased at 1.4V. f = 1 MHz, TA 3. IDD is dependent on output loading and cycle rates.Specified values are obtained with mini-mum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0C 70C) is TA ensured. 6. An initial pause of 100s is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VCC and VCCQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a mono-tonic manner. 9. Outputs measured at 1.5V with equivalent load:
WED3DG7264V-D1
PRELIMINARY
Q 50pF
10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point. 12. Other input signals are allowed to transition no more than once every two clocks and are other-wise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate.
16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The IDD current will increase or decrease in a proportional amount by the amount the frequency is altered for the test condition. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 7.5ns for 75/10 and 7. 22. VIH overshoot: VIH (MAX) = VCCQ + 2V for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL under-shoot: VIL (MIN) = -2V for a pulse width 3ns. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/7ns after the first clock delay, after the last WRITE is executed. 25. Precharge mode only. 26. JEDEC and PC100, PC133 specify three clocks. 27. tAC for 75/10/7 at CL = 3 with no load is 4.6ns and is guaranteed by design. 28. Parameter guaranteed by design. 29. For 75/10, CL = 3, tCK = 7.5ns; For 7, CL = 2, tCK = 7.5ns 30. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 4 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
PACKAGE DIMENSIONS FOR D1
Ordering Information WED3DG7264V10D1 WED3DG7264V7D1 WED3DG7264V75D1 Speed 100MHz 133MHz 133MHz CAS Latency CL=2 CL=2 CL=3
WED3DG7264V-D1
PRELIMINARY
Height* 31.75 (1.25") MAX 31.75 (1.25") MAX 31.75 (1.25") MAX
NOTES: * Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
PACKAGE DIMENSIONS FOR D1
67.72 (2.661 Max) 2.01 (0.079 Min) 6.48 (0.255) MAX
WEDC
3.99 (0.157)
31.75 (1.25) Max 19.99 (0.787)
4.01 (0.158) MIN
32.79 (1.291) 23.14 (0.913) 4.60 (0.181) 28.2 (1.112) 1.50 (0.059) 3.20 (0.126) MIN 0.99 0.10 (0.039 0.004)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 4 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Document Title
512MB - 2x32Mx72 SDRAM, UNBUFFERED w/PLL
WED3DG7264V-D1
PRELIMINARY
Revision History Rev #
Rev 0 Rev 1 Rev 2
History
Created Datasheet Updates 2.1 Added series resistors 2.2 Corrected block diagram 2.3 Added package JD1 option 2.4 Added lead-free and RoHS notes 2.5 Provided source control option 2.6 Availability of industrial temperature 2.7 Moved from Advanced to Preliminary 2.8 Updated laminate diagram
Release Date
10-00 10-02 3-05
Status
Advanced Advanced Preliminary
Rev 3
3.1 Updated CAP specs 3.2 Updated IDD specs
5-05
Preliminary
Rev 4
4.1 Removed JD1 option, not supported with this PCB
7-05
Preliminary
White Electronic Designs Corp. reserves the right to change products or specifications without notice. July 2005 Rev. 4 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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